Embodiments relate generally to microprocessors, and, more particularly, to adaptive power ramp control in microprocessors.
High-frequency voltage droop, sometimes called “LdI/dt” droop, can manifest in microprocessors (e.g., and other very-large-scale integration (VLSI) circuits, and the like), because of effects of inductance (L) in power distribution networks (PDN) of the circuits, combined with sudden power and/or current fluctuations (dI/dt). For example, some state-of-the-art microprocessors have been shown to experience voltage droops of around 80 mV within a few nanoseconds. This phenomenon can be found in high-performance microprocessors and also in lower-power embedded processors (e.g. mobile platforms, such as smart phones, tablet computers, etc.), which can include economic packages having relatively large inductances. As microprocessor complexities increase, both dI/dt and L tend to increase from one generation to another, which can manifest increasingly severe high-frequency voltage droops.
Such voltage droops can affect circuit timing, including potentially causing critical path timing failures. Some traditional approaches seek to avoid critical path timing failures during LdI/dt voltage droop by designing microprocessors with large operational margins (e.g., voltage guardbands), for example, as part of a voltage regulator module (VRM). Increasing operational margins often involves sacrificing power and performance. Other traditional approaches seek to suppress voltage fluctuations, which can allow the microprocessors to perform reliably with a smaller voltage guardband, thereby permitting use of lower VRM supply voltages to save power and/or permitting boosting to higher frequencies to improve performance. Both reduced power and increased performance are considered important metrics in microprocessors design. However, such traditional approaches tend to be of little effect or are effective only in limited frequency ranges.